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GF9320 Scaling Processor
GF9320 Data Sheet Features
* * * * * * * * * * * * * * * * broadcast quality 10 / 8-bit 24-tap poly-phase horizontal and vertical scalar for HDTV / SDTV video images high performance 2D scaling processor with separate control of horizontal and vertical scaling factors and pan positions support for arbitrary video formats up to 2048 by 2048 support for multiplexed and non-multiplexed Y/C video flexible 4:2:2 or 4:4:4 YCbCr or RGB output field merge / separation can be inserted / removed from progressive images using interlaced I/O double banked control registers for 'on-the-fly' dynamic effects external 3:2 / 2:2 pull-down insertion and extraction programmable output matrix with 6dB gain range film rate features include 1080p24 and 1080PsF support fully programmable colour background generator flexible F,V,H output and TRS insertion seamless interface to GF9330 de-interlacer seamless interface to common SDRAM user configuration through dedicated serial interface 3.3V supply
choices while a programmable colour background generator can be customized to appropriately match the image content. A fully programmable and flexible output matrix allows for colour difference over-sampling, gain and hue controls as well as YCbCr to RGB conversions to power nearly any display device on the market. The GF9320 also includes a vertical interpolation filter to perform stand alone cost-sensitive de-interlacing. Broadcast quality de-interlacing is offered through a seamless interface to the GF9330 and GF9331 devices. Applications
* * * * * * * * HDTV Up / Down Converters Production Equipment Video Walls Projection Systems Plasma Displays LCD TVs Home Theatre Systems HD DVD Players
Description The GF9320 Scaling Processor offers 10 / 8-bit broadcast quality scaling of video images up to 2048 by 2048 pixels. The GF9320 supports arbitrary display modes to fit custom applications. Dynamic zoom and pan effects allow for a variety of aspect ratio conversion
Ordering Information
Part Number
GF9320-CBW
Package
352 pin TBGA
Temp. Range
0oC to 70oC
YC/Y C
Input Processing
MUX
Horizontal Scaling Filter
MUX
Input Processing
G/Y/YC B/Cb/C R/Cr
CTRL
Control Interface
MUX
External Memory Interface 1
Vertical Scaling Filter
External Memory Interface 2
Block Diagram
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GF9320 Data Sheet
Contents
Features ........................................................................................................................1 Description ....................................................................................................................1 Applications...................................................................................................................1 Ordering Information .....................................................................................................1 1. Pin Description ..........................................................................................................3 2. Electrical Characteristics ...........................................................................................7 3. Detailed Device Description ....................................................................................11 3.1 Device Overview ...........................................................................................11 3.2 Serial Interface Control .................................................................................12 3.3 Input Processing ...........................................................................................21 3.4 Scaling Processor .........................................................................................22 3.5 SDRAM Memory Interface ............................................................................34 3.6 Output Processor ..........................................................................................57 3.7 Output Timing Control ...................................................................................58 4. Package Dimensions ..............................................................................................59 5. Revision History ......................................................................................................60
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GF9320 Data Sheet
1. Pin Description
1
ADDR_A5
2
3
4
CS_A0
5
CS_A2
6
WE_A
7
NC
8
DATA_A0
9
DATA_A4
10
DATA_A6
11
VDD
12
13
14
15
16
17
ADDR_B6
18
NC
19
BA_B
20
GND
21
CKEN_B
22
CS_B3
23
DATA_B0
24
DATA_B3
25
DATA_B6
26
DATA_B7
ADDR_A7 ADDR_A10
DATA_A12 DATA_A14
DATA_A15 DATA_A19 ADDR_B2
A
ADDR_A4 ADDR_A6 ADDR_A8 GND CS_A1 CAS_A NC CKEN_A DATA_A3 DATA_A5 GND DATA_A11 DATA_A13 DATA_A16 GND ADDR_B3 ADDR_B7 ADDR_B8 RAS_B CK_B CS_B0 DATAEN_AB DATA_B1 DATA_B5 DATA_B8 DATA_B9
B
ADDR_A1 ADDR_A3 VDD ADDR_A9 VDD RAS_A VDD GND DATA_A2 VDD DATA_A8 DATA_A10 VDD DATA_A17 ADDR_B0 ADDR_B4 VDD ADDR_B9 CAS_B VDD CS_B1 GND DATA_B4 VDD DATA_B10 DATA_B12
C
NC NC ADDR_A2 GND BA_A CS_A3 GND CK_A DATA_A1 GND DATA_A7 DATA_A9 GND DATA_A18 ADDR_B1 ADDR_B5 GND ADDR_B10 WE_B GND CS_B2 DATA_B2 GND DATA_B11 GND DATA_B14
D
OUT_FRST NC NC ADDR_A0 DATA_B13 VDD DATA_B15 DATA_B16
E
RST NC NC NC DATA_B17 DATA_B18 DATA_B19 NC
F
GND CK_IN VDD GND GND VDD CK_V GND
G
YIN9 FILM_FR GND NC NC NC NC NC
H
YIN5 YIN6 YIN7 YIN8 NC NC GND OUT_CK
J
YIN3 YIN4 VDD GND GND VDD GOUT9 GOUT8
K
CIN9 YIN0 YIN1 YIN2
L
CIN5 CIN6 CIN7 CIN8
TOP VIEW
GF9320 PIN OUT 352 TBGA
VDD: +3.3V GND: 0V
GOUT7
GOUT6
GOUT5
GOUT4
GOUT3
GND
GOUT2
GOUT1
M
CIN1 CIN2 CIN3 CIN4
GND
VDD
GOUT0
NC
N
CIN0 NC VDD GND BOUT6 BOUT7 BOUT8 BOUT9
P
GND GND GND GND
BOUT4
GND
VDD
BOUT5
R
OUT_H OUT_V OUT_F NC
BOUT0
BOUT1
BOUT2
BOUT3
T
NC NC VDD GND
NC: No Connection
GND VDD ROUT8 ROUT9
U
SIF_IN SIF_CK SIF_RST SIF_OUT ROUT5 ROUT6 ROUT7 NC
V
NC NC NC NC ROUT1 ROUT2 ROUT3 ROUT4
W
VDD VDD VDD GND GND VDD NC ROUT0
Y
TOUT1 TOUT2 NC NC DATA_D18 DATA_D19 GND CK_OUT
AA
NC NC NC ADDR_C1 DATA_D13 GND DATA_D16 DATA_D17
AB
NC ADDR_C0 ADDR_C3 GND GND CAS_C GND DATA_C1 VDD GND DATA_C7 DATA_C11 DATA_C14 GND ADDR_D1 ADDR_D5 GND BA_D WE_D GND CS_D3 DATA_D2 GND DATA_D11 DATA_D14 DATA_D15
AC
ADDR_C2 ADDR_C4 VDD ADDR_C10 CS_C1 RAS_C VDD DATA_C2 NC VDD DATA_C8 DATA_C12 DATA_C15 VDD ADDR_D0 ADDR_D4 VDD ADDR_D10 CAS_D VDD CS_D2 GND DATA_D4 VDD DATA_D10 DATA_D12
AD
ADDR_C5 ADDR_C6 ADDR_C9 CS_C0 CS_C3 GND CKEN_C DATA_C3 NC DATA_C5 DATA_C9 GND DATA_C16 DATA_C19 NC ADDR_D3 ADDR_D7 ADDR_D9 RAS_D CK_D CS_D1 DATAEN_CD DATA_D1 DATA_D5 DATA_D7 DATA_D9
AE
ADDR_C7 ADDR_C8 BA_C CS_C2 WE_C CK_C DATA_C0 DATA_C4 NC DATA_C6 DATA_C10 DATA_C13 DATA_C17 DATA_C18 NC ADDR_D2 ADDR_D6 ADDR_D8 CKEN_D GND CS_D0 VDD DATA_D0 DATA_D3 DATA_D6 DATA_D8
AF
Figure 1-1: GF9320 Pin Out
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GF9320 Data Sheet
Table 1-1: Pin Descriptions Symbol
YIN[9:0]
Pin Grid
H1, J4, J3, J2, J1, K2, K1, L4, L3, L2
Type
I
Description
10-bit multiplexed signed luminance / signed offset colour difference data input. Note that either input must include TRS words.
CIN[9:0]
L1, M4, M3, M2, M1, N4, N3, N2, N1, P1 G2
I
10-bit signed offset colour difference data input. Note that theinput must include TRS words.
CK_IN
I
Input clock. Note that it is equal Y data rate for separate Y and C inputs, and is equal to 2x Y data rate for multiplexed YC input.
CK_V
G25
I
Vertical processing clock. Note that it is usually the higher of CK_IN or CK_OUT.
CK_OUT FILM_FR OUT_FRST GOUT[9:0]
AA26 H2 E1 K25, K26, L23, L24, L25, L26, M23, M25, M26, N25
I I I O
Output clock. Input film sequence reset. Output frame reset. 10 / 8-bit unsigned green data output OR 10 / 8-bit unsigned luminance data output OR 10 / 8-bit multiplexed signed luminance / signed offset colour difference data output.
BOUT[9:0]
P26, P25, P24, P23, R26, R23, T26, T25, T24, T23
O
10 / 8-bit unsigned blue data output OR 10 / 8-bit signed offset (B-Y) data output OR 10/8-bit multiplexed signed offset colour difference data output.
ROUT[9:0]
U26, U25, V25, V24, V23, W26, W25, W24, W23, Y26 J26 T3
O
10 / 8-bit unsigned red data output OR 10 / 8-bit signed offset (R-Y) data output.
OUT_CK OUT_F
O O
Output clock timed to clock output data. Output format frame / field signal. Note that the output is 3 clocks in advance of output video data.
OUT_V
T2
O
Output format vertical signal. Note that the output is 3 clocks in advance of output video data.
OUT_H
T1
O
Output format horizontal signal. Note that the output is 3 clocks in advance of output video data.
SIF_OUT SIF_IN SIF_CK SIF_RST RST DATA_A[19:0]
V4 V1 V2 V3 F1 A15, D14, C14, B14, A14, A13, B13, A12, B12, C12, D12, C11, D11, A10, B10, A9, B9, C9, D9, A8
O I I I I I/O
Serial interface control data out. Serial interface control data in. Serial interface clock. Serial interface reset. Power-on reset. Data bus for memory array A.
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GF9320 Data Sheet
Table 1-1: Pin Descriptions (Continued) Symbol
DATA_B[19:0]
Pin Grid
F25, F24, F23, E26, E25, D26, E23, C26, D24, C25, B26, B25, A26, A25, B24, C23, A24, D22, B23, A23 AE14, AF14, AF13, AE13, AD13, AC13, AF12, AD12, AC12, AF11, AE11, AD11, AC11, AF10, AE10, AF8, AE8, AD8, AC8, AF7 AA24, AA23, AB26, AB25, AC26, AC25, AB23, AD26, AC24, AD25, AE26, AF26, AE25, AF25, AE24, AD23, AF24, AC22, AE23, AF23 A3, C4, B3, A2, B2, A1, B1, C2, D3, C1, E4 D5 D18, C18, B18, B17, A17, D16, C16, B16, A16, D15, C15 A19 AD4, AE3, AF2, AF1, AE2, AE1, AD2, AC3, AD1, AB4, AC2 AF3 AD18, AE18, AF18, AE17, AF17, AC16, AD16, AE16, AF16, AC15, AD15 AC18 D6, A5, B5, A4 A22, D21, C21, B21 AE5, AF4, AD5, AE4 AC21, AD21, AE21, AF21 C6 B19 AD6 AE19 B6 C19 AC6
Type
I/O
Description
Data bus for memory array B.
DATA_C[19:0]
I/O
Data bus for memory array C.
DATA_D[19:0]
I/O
Data bus for memory array D.
ADDR_A[10:0] BA_A ADDR_B[10:0]
O O O
Address bus for memory array A. SDRAM bank select for memory array A. Address bus for memory array B.
BA_B ADDR_C[10:0]
O O
SDRAM bank select pin for memory array B. Address bus for memory array C.
BA_C ADDR_D[10:0]
O O
SDRAM bank select pin for memory array C. Address bus for memory array D.
BA_D CS_A[3:0] CS_B[3:0] CS_C[3:0] CS_D[3:0] RAS_A RAS_B RAS_C RAS_D CAS_A CAS_B CAS_C
O O O O O O O O O O O O
SDRAM bank select pin for memory array D. Chip select for memory array A. Chip select for memory array B. Chip select for memory array C. Chip select for memory array D. Row address strobe for memory array A. Row address strobe for memory array B. Row address strobe for memory array C. Row address strobe for memory array D. Column address strobe for memory array A. Column address strobe for memory array B. Column address strobe for memory array C.
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GF9320 Data Sheet
Table 1-1: Pin Descriptions (Continued) Symbol
CAS_D WE_A WE_B WE_C WE_D CK_A CK_B CK_C CK_D CKEN_A CKEN_B CKEN_C CKEN_D DATAEN_AB DATAEN_CD VDD
Pin Grid
AD19 A6 D19 AF5 AC19 D8 B20 AF6 AE20 B8 A21 AE7 AF19 B22 AE22 K3, C10, A11, P3, C13, U3, C17, Y3, C20, AD3, G3, AD7, AC9, AD10, AD14, AD17, C24, AD20, AF22, AD24, E24, Y24, G24, K24, C5, N24, C3, U24, R25, C7, Y1, Y2 R24, U23, N23, K23, G26, G23, Y23, D25, AC20, AF20, AC17, D23, AC14, AC10, AC7, AC5, AC4, D20, A20, Y4, D17, B15, U4, D13, P4, B11, D10, K4, D7, G4, B4, D4, AC23, C8, H3, J25, AE6, C22, AE12, M24, AD22, G1, AB24, AA25, R1, R2, R3, R4 H26, W2, W3, J23, W4, T4, U1, U2, J24, A7, A18, AA3, AA4, W1, AB1, AB2, F26, AC1, AB3, N26, Y25, F2, V26, F3, P2, B7, D2, AD9, E3, H24, AE9, D1, AF9, E2, AE15, AF15, F4, H23, H25, H4, AA1, AA2
Type
O O O O O O O O O O O O O O O I
Description
Column address strobe for memory array D. Write enable for memory array A. Write enable for memory array B. Write enable for memory array C. Write enable for memory array D. Clock for memory array A. Clock for memory array B. Clock for memory array C. Clock for memory array D. Clock enable for memory array A. Clock enable for memory array B. Clock enable for memory array C. Clock enable for memory array D. Data enable for memory arrays A and B. Data enable for memory arrays C and D. 3.3V supply.
GND
I
Device ground.
NC
No connection.
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GF9320 Data Sheet
2. Electrical Characteristics
Table 2-1: Absolute Maximum Ratings Parameter
Power Supply Voltage Input Voltage Output Voltage Output Current Operating Temperature Storage Temperature
Symbol
VDD VI VO IO TA TSTG
Conditions
Rated Value
-0.5 to +4.6
Units
V V V mA
oC o
VI < VDD + 0.5 V VO < VDD + 0.5 V
-0.5 to +4.6 -0.5 to +4.6 40 0 to +70 -65 to +150
C
Table 2-2: Recommend Operating Conditions Parameter
Power Supply Voltage High-Level Input Voltage Low-Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Input Rise Time Input Fall Time
Symbol
VDD VIH VIL VP VN VH tri tfi
Conditions
Min.
3.0
Typ.
3.3 -
Max.
3.6 VDD 0.8 2.7 1.4 1.5 200 200
Units
V V V V V V ns ns
TTL Interface TTL Interface
2.0 0.0 1.5 0.6 1.1
Normal Input Normal Input
0 0
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GF9320 Data Sheet
Table 2-3: DC Characteristics VDD = 3.0 to 3.6V, TA = 0 to 70oC, unless otherwise shown Parameter
Static Current Consumption Input Leakage Current Low-Level Output Current High-Level Output Current Low-Level Output Voltage High-Level Output Voltage Off-State Output Current Output Short-Circuit Current
Symbol
IDDS II IOL IOH VOL VOH IOZ IOS
Conditions
VI = VDD or GND VI = VDD or GND VOL = 0.4V VOH = 2.4V IOL = 0 mA IOH = 0 mA VO = VDD or GND VO = GND
Min.
Typ.
10 10-4
Max.
200 10 0.1 10 -250
Units
A A mA mA V V A mA
12.0 -2.0 VDD - 0.1 -
-
Table 2-4: Capacitance TA = 25oC; =1MHz Parameter
Input Capacitance Output Capacitance I/O Capacitance
Symbol
CI CO CIO
Conditions
Min.
4.0 4.0 4.0
Typ.
-
Max.
6.4 6.0 6.0
Units
pF pF pF
Table 2-5: Operating Current VDD = 3.0 to 3.6V, TA = 0 to 70oC, unless otherwise shown Parameter
Operating Current
Symbol
ICC
Conditions
CK_IN @ 90MHz CK_OUT @ 90MHz CK_V @ 88MHz
Min.
-
Typ.
-
Max.
910
Units
mA
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GF9320 Data Sheet
Table 2-6: AC Characteristics - Setup & Hold Times VDD = 3.0 to 3.6V, TA = 0 to 70oC, unless otherwise shown Signal Name Min.
YIN[9:0] CIN[9:0] FILM_FR SIF_IN SIF_RST OUT_FRST DATA_A DATA_B DATA_C DATA_D 2 2 1 1 1 2 2 2 2
Setup Max.
-
Hold Min.
1 1 2 2 2 2 0 0 0 0
Reference Clock Max.
CK_IN CK_IN CK_IN SIF_CK SIF_CK CK_OUT CK_A CK_B CK_C CK_D
Units
ns ns ns ns ns ns ns ns ns ns
Table 2-7: AC Characteristics - Pulse Signal VDD = 3.0 to 3.6V, TA = 0 to 70oC, unless otherwise shown Signal Name Pulse Width Min.
RST 110a
Units
Max.
s
a.The minimum pulse width is for 64Mb SDRAMs. If 16Mb is used them 10s width can be used.
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GF9320 Data Sheet
Table 2-8: Output Signal Timing Specifications Signal Name CLK to Valid Output Delay Min. (ns)
OUT_CK GOUT[9:0] BOUT[9:0] ROUT[9:0] ADDR_A, RAS_A, CAS_A, WE_A, CKEN_A, DATA_A ADDR_B, RAS_B, CAS_B, WE_B, CKEN_B, DATA_B ADDR_C, RAS_C, CAS_C, WE_C, CKEN_C, DATA_C ADDR_D, RAS_D, CAS_D, WE_D, CKEN_D, DATA_D 1.81 0.15 0.15 0.15 1.25 1.25 1.25 1.25
Reference Clock
Max. (ns)
3.97 3 3 3 6 6 6 6 CK_OUT OUT_CK OUT_CK OUT_CK CK_A CK_B CK_C CK_D
Table 2-9: Clock Frequency Clock Name Min. (MHz)
CK_IN CK_V CK_OUT SIF_CK 1 1 1 -
Frequency Max. (MHz)
90 88 90 90
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GF9320 Data Sheet
3. Detailed Device Description
3.1 Device Overview
A system level block diagram is shown in the "Block Diagram" on page 1. 2D scaling is performed by cascading two 1D-scaling filters. If the number of horizontal input samples is greater than the number of horizontal output samples (i.e. down sampling), then it is advantageous to perform horizontal resizing first. Otherwise, horizontal resizing is performed last. This minimizes the number of operations required, reduces the intermediate image size and thus lowers the SDRAM requirements. In addition, the SDRAMs are used for field merge or separation operations to perform simple frame rate conversions (e.g. 30 60 and 48 60) for film applications. This minimizes the on chip memory required to perform 2D format conversion for low-cost, high-quality format conversion. The GF9320 has 2 fields / frames of delay depending on the selected operating mode. Processing is performed simultaneously on 3 fields / frames. Input processing is performed on field / frame N, vertical processing is performed on field / frame (N1) and output processing is performed on field / frame (N-2). The input processor decodes the input TRS to determine input video timing information. An area of the input video is selected according to the downloaded parameters. The input video is resized horizontally if down sampling is indicated. The video is passed to picture memory control #1 and stored in SDRAM. Field / frame (N-1) is read out of picture memory #1, processed vertically, and stored in picture memory #2. To process the video vertically the read address to picture memory #1 transposes the video data while the write address to picture memory #2 transposes the video data back. This transpose operation allows the vertical processing to be done as rows instead of columns. Field / frame (N-2) is read out of picture memory #2 and resized horizontally if up sampling is indicated. The flexible output processor can be selected to perform 4:2:2 to 4:4:4 colour difference over sampling, YCbCr to RGB conversion, colour background insertion and output TRS insertion.
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GF9320 Data Sheet
3.2 Serial Interface Control
The serial interface download control parameters are grouped into 5 sets as given in Table 3-1: Serial Interface Download Groups. All parameters may be downloaded at once or each set can be downloaded individually. This grouping allows for quick downloading of dynamic parameters (e.g. zoom, pan, gain, etc.) and only requires that the static parameters be downloaded once. Details of individual control parameters are provided in Table 3-2: Serial Interface Download Parameters.
Table 3-1: Serial Interface Download Groups Name
All Parametersa
CMD ID
0 00000000b
No. of Bytes
147
Number of Bits
1176
Description
A download of all parameters.
Word
AP[1175:0]
I/O Format Parameters
1 00100000b 2 01000000 3 01100000 4 10000000b 5 10100000b
b b
11
7 + 14 + 66 + 1 (fill) = 88
Input and static output parameters. These parameters tend to remain fixed once the input and output format is selected. Resizing parameters. These parameters change with zoom, pan, and crop controls.
IO[87:0]
Scaling Parameters
19
149 + 3 (fill) = 152
RS[151:0]
Dynamic Output Parameters
20
157 + 3 (fill) = 160
Dynamic output parameters. These parameters change with gain, H position, line advance, etc...
OD[159:0]
Horizontal Filter Coefficients Vertical Filter Coefficients
43
344 + 0 (fill) = 344
Horizontal filter.
HF[343:0]
54
428 + 4 (fill) = 432
Vertical filter.
VF[431:0]
a. The GF9320 download parameters are grouped into 5 sets. b.Each group will be extended with zeros to make an integer number of bytes. In each group the LSB is sent first. So, for instance, the I/ O format parameter group sends 1 zero followed by the PROC_8_BITS bit followed by the OUT_8_BITS bit. A download of all parameters (CMD ID = 0) sends the word: AP[1175:0] = IO[87:0] | RS[151:0] | OD[159:0] | HF[343:0] | VF[431:0] where "|" represents concatenation. As with all other words the LSB of AP[1175:0] is sent first. The CMD_ID word is listed above in binary form from MSB to LSB. As with all other words the CMD_ID is sent LSB first. For example, a download of the dynamic output parameters (CMD_ID=3) sends 5 zeros followed by 2 ones followed by 1 zero followed by OD0 followed by OD1 followed by OD2....OD159. Note that all CMD_IDs have 5 zeros as the 5 least significant bits so that each download command starts with 5 zeros.
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters Parameter Name
I/O Format Parameters Input Format Parameters IN_PROGRESSIVE
No. Of Bits
88 Total 7 Sub-total 1
Description
Word Position
Used By
Time Frame
Indicates that the input is progressive. 0 - Interlaced 1 - Progressive
IO[87]
Input Control
0
IN_TOP_ACT_FLD
1
Used for interlaced formats only. Indicates which field contains the first active line in a frame. (i.e. which field is on top) 0 - Field 0 is on top 1 - Field 1 is on top
IO[86]
Input Control
0
IN_TOP_ACT_LONGER
1
Used for interlaced formats only. Indicates if the top field is one line longer than the bottom field. 0 - Top and Bottom fields contain the same number of active lines 1 - Top field has one more active line
IO[85]
Input Control
0
IN_YC_MUXED
1
Indicates if the input bus is one 10-bit bus for muxed Y&C data. 0 - Two 10-bit buses for Y and CbCr 1 - Y & C Muxed data on a 10-bit bus
IO[84]
Input Control
0
IN_FILM_RATE
2
Input film frame rate. Used for film inputs only. 00 - Input is from film with 3:2 pull-down 01 - Input is from film with 2:2 pull-down 10 - Input is at film rate (24/25 Hz) 11 - Not from film
IO[83:82]
Input Control
0
IN_REFR_LEFT
1
This indicates a left memory array refresh is required and normally indicates that the input is from film. 0 - No refresh 1 - Refresh
IO[81]
Memory Control
0
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Memory Configuration MEM_CONFIG_LEFT
No. Of Bits
14 Sub-total 2
Description
Word Position
Used By
Time Frame
Indicates the number of SDRAMs per array in the left bank excluding chips needed for LSBs if necessary. (i.e. 8-bit processing) 00 - 4 chips 01 - 3 chips 10 - 2 chips 11 - 1 chip
IO[80:79]
Memory Control
0
MODE_16_LEFT
1
Maximum number of left bank SDRAM memory rows used to store a horizontal active line. 0 - 8 memory rows 1 - 16 memory rows
IO[78]
Memory Control
0
MEM_CONFIG_RIGHT
2
Indicates the number of SDRAMs per array in the right bank excluding chips needed for LSBs if necessary. (i.e. 8 bit processing) 00 - 4 chips 01 - 3 chips 10 - 2 chips 11 - 1 chip
IO[77:76]
Memory Control
0
MODE_16_RIGHT
1
Maximum number of right bank SDRAM memory rows used to store a horizontal active line. 0 - 8 memory rows 1 - 16 memory rows
IO[75]
Memory Control
0
PIX2READ
7
Number of pixels to be pre-read. Vertical processing requires prereading samples so that no hits occur while processing a column of data. This indicates a right memory array refresh is required and normally indicates that the input is from film. 0 - No refresh 1 - Refresh
IO[74:68]
Memory Control
0
OUT_REFR_RIGHT
1
IO[67]
Memory Control
0
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Static Output Format Parameters OUT_HLEN_TOT OUT_VLEN_TOT OUT_HLEN_ACT
No. Of Bits
67 Sub-total 12 12 11
Description
Word Position
Used By
Time Frame
The total number of samples per line. (e.g. 2200) The total number of output lines in a frame. (e.g. 1125) The number of active samples per line minus 1. (e.g. 1919 implies 1920 active samples) The number of active output lines minus 1. (e.g. 1079 implies 1080 active lines) Indicates that the output is progressive. 0 - Interlaced 1 - Progressive
IO[66:55] IO[54:43] IO[42:32]
Output Timing Output Timing Output Timing Output Timing Output Timing / Input Control Output Timing
0 0 0
OUT_VLEN_ACT
11
IO[31:21]
0
OUT_PROGRESSIVE
1
IO[20]
0
OUT_TOP_ACT_FLD
1
Used for interlaced formats only. Indicates which field contains the first active line in a frame. (i.e. which field is on top) 0 - Field 0 is on top 1 - Field 1 is on top
IO[19]
0
OUT_TOP_ACT_LONGER
1
Used for interlaced formats only. Indicates if the top field is one line longer than the bottom field. 0 - Both fields have the same number of active lines 1 - Top field has one more active line
IO[18]
Output Timing
0
OUT_VACT_POS
8
The position of the first active output line relative to the start of the frame. For interlaced inputs this implies field 0.
IO[17:10]
Output Timing
0
OUT_FLD_LONGER
1
Used for interlaced formats only. Indicates which field is longer. Interlaced formats contain an odd number of lines. So one field contains more lines. 0 - Field 0 is longer 1 - Field 1 is longer
IO[9]
Output Timing
0
OUT_REF
1
0 - Input TRS 1 - Output Reset pin on GF9320 (OUT_FRST)
IO[8]
Output Timing
0
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
OUT_FILM_RATE
No. Of Bits
2
Description
Output film frame rate. 00 - Output has a 3:2 pull-down sequence 01 - Output has a 2:2 pull-down sequence 10 - Output is at a film rate (24/25 Hz) 11 - Output is not to a film rate or sequence
Word Position
IO[7:6]
Used By
Output Timing / Input Control
Time Frame
0
OUT_MODE
2
Indicates output port configuration. 00 - 4:4:4 GBR Triple output 01 - 4:4:4 YCbCr Triple output 10 - 4:2:2 YCbCr Muxed single output 11 - 4:2:2 YCbCr Muxed dual output
IO[5:4]
Output
0
OUT_TRS_ON
1
Indicates if TRS is inserted into the output. 0 - TRS not inserted 1 - TRS inserted
IO[3]
Output
0
OUT_8_BITS
1
Indicates that the output is rounded to 8 bits. 0 - 10-bit output 1 - 8-bit output
IO[2]
Output
0
PROC_8_BITS
1
Indicates that H&V processing is rounded to 8-bits. 0 - 10-bit processing (Requires LSB memory) 1 - 8-bit processing
IO[1]
Int. Filters
0
IO_FILL
1
Not used.
IO[0]
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Resizing Parameters H_PROC_FIRST
No. Of Bits
152 Total 1
Description
Word Position
Used By
Time Frame
Indicates horizontal processing is performed first. 0 - Horizontal processing last (H_ZOOM_RATIO < 524288) 1 - Horizontal processing first (H_ZOOM_RATIO >= 524288)
RS[151]
Glue Logic (Mux) / Mem Control
1 2
H_FLT_DEC
1
Horizontal filter decimate. 0 - Non-decimate mode 1 - Decimate mode
RS[150]
H Control / HBL Filter
1/3 1/3
H_ZOOM_RATIO
22
Horizontal zoom ratio. IN_HLIVE 524288 ------------------------------------------------OUT_HLIVE if H_FLT_DEC = 0 IN_HLIVE 524288 ------------------------------------------------OUT_HLIVE 2 if H_FLT_DEC = 1
RS[149:128]
H Control
1/3
IN_HSTART_PHASE IN_HSTART
7 11
Indicates the starting horizontal phase to be used for resampling. Indicates the first sample to be used for resampling.
RS[127:121] RS[120:110]
H Control Input Timing / H Control / Mem Control Input Timing / H Control / Mem Control Output Timing / H Control / Mem Control Output Timing / H Control / Mem Control VBL Filter
1/3 1 1/3 2 1 1/3 2 3 1/3 2 3 1/3 2 2
IN_HSTOP
11
Indicates the last sample to be used for resampling.
RS[109:99]
OUT_HSTART
11
Indicates the placement of the first output sample with live data. This value must be even.
RS[98:88]
OUT_HSTOP
11
Indicates the placement of the last output sample with live data. This value must be odd.
RS[87:77]
V_FLT_DEC
1
Vertical filter decimate. 0 - Non-decimate mode 1 - Decimate mode
RS[76]
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
V_ZOOM_RATIO
No. Of Bits
22
Description
Vertical zoom ratio. IN_VLIVE 524288 ------------------------------------------------OUT_VLIVE if V_FLT_DEC = 0 IN_VLIVE 524288 ------------------------------------------------OUT_VLIVE 2 if V_FLT_VLIVE = 1
Word Position
RS[75:54]
Used By
V Control
Time Frame
2
IN_VSTART_PHASE IN_VSTART
7 11
Indicates the starting vertical phase to be used for resampling. Indicates the first line to be used for resampling. Indicates the last line to be used for resampling. Indicates the placement of the first output line with live data. Indicates the placement of the last output line with live data. Not used.
RS[53:47] RS[46:36]
V Control Input Timing / V Control Input Timing / V Control Output Timing / V Control Output Timing / V Control
2 1 2 1 2 3 2 3 2
IN_VSTOP
11
RS[35:25]
OUT_VSTART
11
RS[24:14]
OUT_VSTOP
11
RS[13:3]
RS_FILL Dynamic Output Parametersa Matrix Coefficients
3 160 Total 117 Sub-total
RS[2:0]
The matrix coefficient format is 2.10. (i.e. 1 sign bit, 2 integer bits and 10 fractional bits) G1 13 Matrix coefficient. G = G1*Y + G2*Cb + G3*Cr G2 13 Matrix coefficient. G = G1*Y + G2*Cb + G3*Cr G3 13 Matrix coefficient. G = G1*Y + G2*Cb + G3*Cr B1 13 Matrix coefficient. B = B1*Y + B2*Cb + B3*Cr B2 13 Matrix coefficient. B = B1*Y + B2*Cb + B3*Cr B3 13 Matrix coefficient. B = B1*Y + B2*Cb + B3*Cr R1 13 Matrix coefficient. R = R1*Y + R2*Cb + R3*Cr OD[81:69] Output 1 OD[94:82] Output 1 OD[107:95] Output 1 OD[120:108] Output 1 OD[133:121] Output 1 OD[146:134] Output 1 OD[159:147] Output 1
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
R2
No. Of Bits
13
Description
Matrix coefficient. R = R1*Y + R2*Cb + R3*Cr
Word Position
OD[68:56]
Used By
Output
Time Frame
1
R3
13
Matrix coefficient. R = R1*Y + R2*Cb + R3*Cr
OD[55:43]
Output
1
Background Colour Y_BKGD
24 Sub-total 8 Background colour for Y. Unsigned integer. OD[42:35] Output 1
CB_BKGD
8
Background colour for Cb. Signed integer.
OD[34:27]
Output
1
CR_BKGD
8
Background colour for Cr. Signed integer.
OD[26:19]
Output
1
Output Timing LINE_ADV H_POS OD_FILL Filter Coefficients Horizontal Filter H_Y_FLT_COEF HYBANK: 12|12|11|10|10|9|9|9|9|8|8 = 107 2 filters * (107 bits) = 214 H_C_FLT_COEF HCBANK: 12|11|9|9|8|8|8 = 65 2 filters * (65 bits) = 130 Vertical Filter V_Y_FLT_COEF HYBANK: 12|12|11|10|10|9|9|9|9|8|8 = 107 2 filters * (107 bits) = 214 V_C_FLT_COEF HCBANK: 12|12|11|10|10|9|9|9|9|8|8 = 107 2 filters * (107 bits) = 214 VYF_FILL
19 Sub-total 4 12 3 776 Total 344 Sub-total 214 Horizontal Y filter coefficients. Center coefficient is 1.10. (i.e. 1 sign bit, 1 integer bit and 10 fractional bits) HY[343:130] (See footnoteb) H Y Filter 1 Line advance with respect to input timing. Horizontal position with respect to input timing. Not used. OD[18:15] OD[14:3] OD[2:0] Output Timing Output Timing 0a 0a
130
Horizontal C filter coefficients. Center coefficient is 1.10. (i.e. 1 sign bit, 1 integer bit and 10 fractional bits)
HY[129:0] (See footnote
b)
H C Filter
1
432 Sub-total 214 Vertical Y filter coefficients. Center coefficient is 1.10. (i.e. 1 sign bit, 1 integer bit and 10 fractional bits) VY[431:218] (See footnotec) V Y Filter 1
214
Vertical C filter coefficients. Center coefficient is 1.10. (i.e. 1 sign bit, 1 integer bit and 10 fractional bits)
VY[217:4] (See footnotec)
V C Filter
1
4
Not used.
VY[3:0]
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GF9320 Data Sheet
a.The resizing parameters, dynamic output parameters, and the filter coefficients are adjustable (dynamic). The I/O Format parameters are static, i.e. once an input and output format is selected the I/O format parameters tend to remain fixed. b.HORIZONTAL COEFFICIENT DOWNLOAD FORMAT: HF[343:0] = HYBANK1[106:0] | HYBANK0[106:0] | HCBANK1[64:0] | HCBANK0[64:0] IN NON-DECIMATE MODE (H_FLT_DEC = 0): HYBANK0 contains the coefficients for a 21-tap symmetric FIR filter and HCBANK0 contains the coefficients for a 13-tap symmetric FIR filter. HYBANK1 and HCBANK1 are not used when H_FLT_DEC is 0 and should contain 0s. HYBANK0[106:0] = HYT0[11:0] | HYT1[11:0] | HYT2[10:0] | HYT3[9:0] | HYT4[9:0] | HYT5[8:0] | HYT6[8:0] | HYT7[8:0] | HYT8[8:0] | HYT9[7:0] | HYT10[7:0] HYBANK1[106:0] = 0 HCBANK0[64:0] = HCT0[11:0] | HCT1[10:0] | HCT2[8:0] | HCT3[8:0] | HCT4[7:0] | HCT5[7:0] | HCT6[7:0] HCBANK1[64:0] = 0 IN DECIMATE MODE (H_FLT_DEC = 1): HYBANK0 and HYBANK1 contain the coefficients for a 41-tap symmetric decimation filter while HCBANK0 and HCBANK1 contain the coefficients for a 25-tap symmetric decimation filter. BANK0s contain the center tap (tap 0) and all odd taps (e.g. 1, 3, 5....) while the BANK1s contain a zero and all even taps (e.g. 2, 4, 6....). HYBANK0[106:0] = HYT0[11:0] | HYT1[11:0] | HYT3[10:0] | HYT5[9:0] | HYT7[9:0] | HYT9[8:0] | HYT11[8:0] | HYT13[8:0] | HYT15[8:0] | HYT17[7:0] | HYT19[7:0] HYBANK1[106:0] = "000000000000" | HYT2[11:0] | HYT4[10:0] | HYT6[9:0] | HYT8[9:0] | HYT10[8:0] | HYT12[8:0] | HYT14[8:0] | HYT16[8:0] | HYT18[7:0] | HYT20[7:0] HCBANK0[64:0] = HCT0[11:0] | HCT1[10:0] | HCT3[8:0] | HCT5[8:0] | HCT7[7:0] | HCT9[7:0] | HCT11[7:0] HCBANK1[64:0] = "000000000000" | HCT2[10:0] | HCT4[8:0] | HCT6[8:0] | HCT8[7:0] | HCT10[7:0] | HCT12[7:0] Further information on the horizontal filter coefficients is given in FIR Filter Parameters (3.4.2.2 FIR Filter Parameters). c.VERTICAL COEFFICIENT DOWNLOAD FORMAT: VF[431:0] = VYBANK1[106:0] | VYBANK0[106:0] | VCBANK1[106:0] | VCBANK0[106:0] | "0000" IN NON-DECIMATE MODE (V_FLT_DEC = 0): VYBANK0 and VCBANK0 both contain the coefficients for a 21-tap symmetric FIR filter. VYBANK1 and VCBANK1 are not used when V_FLT_DEC is 0 and should contain 0s. VYBANK0[106:0] = VYT0[11:0] | VYT1[11:0] | VYT2[10:0] | VYT3[9:0] | VYT4[9:0] | VYT5[8:0] | VYT6[8:0] | VYT7[8:0] | VYT8[8:0] | VYT9[7:0] | VYT10[7:0] VYBANK1[106:0] = 0 VCBANK0[106:0] = VCT0[11:0] | VCT1[11:0] | VCT2[10:0] | VCT3[9:0] | VCT4[9:0] | VCT5[8:0] | VCT6[8:0] | VCT7[8:0] | VCT8[8:0] | VCT9[7:0] | VCT10[7:0] VCBANK1[106:0] = 0 IN DECIMATE MODE (V_FLT_DEC = 1): VYBANK0 and VYBANK1 together contain the coefficients for a 41-tap symmetric decimation filter while VCBANK0 and VCBANK1 together also contain the coefficients for a 41-tap symmetric decimation filter. BANK0s contain the center tap (tap 0) and all odd taps (e.g. 1, 3, 5....19) while the BANK1s contain a zero and all even taps (e.g. 2, 4, 6....20). VYBANK0[106:0] = VYT0[11:0] | VYT1[11:0] | VYT3[10:0] | VYT5[9:0] | VYT7[9:0] | VYT9[8:0] | VYT11[8:0] | VYT13[8:0] | VYT15[8:0] | VYT17[7:0] | VYT19[7:0] VYBANK1[106:0] = "000000000000" | VYT2[11:0] | VYT4[10:0] | VYT6[9:0] | VYT8[9:0] | VYT10[8:0] | VYT12[8:0] | VYT14[8:0] | VYT16[8:0] | VYT18[7:0] | VYT20[7:0] VCBANK0[106:0] = VCT0[11:0] | VCT1[11:0] | VCT3[10:0] | VCT5[9:0] | VCT7[9:0] | VCT9[8:0] | VCT11[8:0] | VCT13[8:0] | VCT15[8:0] | VCT17[7:0] | VCT19[7:0] VCBANK1[106:0] = "000000000000" | VCT2[11:0] | VCT4[10:0] | VCT6[9:0] | VCT8[9:0] | VCT10[8:0] | VCT12[8:0] | VCT14[8:0] | VCT16[8:0] | VCT18[7:0] | VCT20[7:0]
The GF9320 parameters are downloaded using a 3-pin serial interface. The serial interface consists of a clock, data and a reset as shown in Figure 3-1: Serial Interface Download Signal Specification. The serial interface reset (SIF_RST) is provided to re-synchronise the download operation in the event that it is interrupted.
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GF9320 Data Sheet
clock can be gated for flow control
SIF_CK
CMD ID (8 bits)
Data Message 1
Stop Bits (>= 7)
CMD ID (8 bits)
Data Message 2
Stop Bits (>= 7)
LSB
MSB LSB
MSB
SIF_IN
1
0
XXX
SERIAL
DATA
1
0
XXX
Data
Held
Data
1
SIF_RST
1) SIF_IN: Serial Data Input. Must be held high (logic 1) if no message is being sent and SIF_CLK is running. First byte sent is the CMD_ID. All data including CMD_ID is sent LSB first. Valid choices for CMD_ID are: LSB ... MSB 01234567 0 (00000000) : A download of all parameters (1176 data bits) 1 (00000100): A download of the I/O parameters (88 data bits) 2 (00000010): A download of the resizing parameters (152 data bits) 3 (00000110): A download of the Dynamic Output parameters (160 data bits) 4 (00000001): A download of the Horizontal Filter coefficients (344 data bits) 5 (00000101): A download of the Vertical Filter coefficients (432 data bits) 2) SIF_CK: Serial Clock. All data from SIF_IN is clocked on the positive edge of SIF_CK. SIF_CK may be held low to pause transmission (i.e. implement flow control). 3) SIF_RST: Message Reset. Active low and asynchronous. Used to recover from a transmission error or message abort. Can be asserted between each message to ensure correct initialization of the download, but is not necessary in general as long as the correct message format (as indicated above) is followed.
Figure 3-1: Serial Interface Download Signal Specification
3.3 Input Processing
The input processor decodes the input TRS from the incoming video stream. This provides input video timing information to the GF9320. An area of the input video data is selected for scaling according to the downloaded parameters (i.e. IN_HSTART, IN_HSTOP, IN_VSTART, and IN_VSTOP). This operation is called the windowing operation. Based on the input field / frame timing and the I/O format parameters a memory enable signal is generated by the input controller. This signal controls the field / frame switching of the SDRAM memory controller. Also, a frame-reset signal is sent to the output controller for use in internal lock mode (OUT_REF=0). The frame reset signal and the field / frame switch point is based on input TRS F-bit in interlaced modes (non-film). Otherwise, (i.e. progressive and all film modes) the frame reset signal and the field / frame switch point is based on one line after input TRS V-bit. Note that in film modes the frame reset signal and field / frame switch point vary according the input and output frame rates.
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GF9320 Data Sheet
3.4 Scaling Processor
At the heart of the GF9320 is the scaling processor. It is here where the raw input image selected from the input video is translated into a raw output image of selected size according to user controlled scaling parameters. As described in 3.1 Device Overview, general 2D scaling is performed by cascading two 1D-scaling filters. This section describes both the horizontal and vertical scaling filters. A block diagram of the horizontal resizing filter is shown in Figure 3-2: Horizontal Scaling Filter. A block diagram of the vertical resizing filter is shown Figure 3-3: Vertical Scaling Filter.
YC
20
Y +10
RANGE ADJUST -512
Y 9.0
21 TAP LOW PASS FILTER OR 41 TAP DECIMATION FILTER
ROUND CLIP (11-BITS)
Y 10.0
24 TAP INTERPOLATION FILTER 128 PHASES
RANGE ADJUST +512
ROUND CLIP (10-BITS)
Y +10
20
YC
YADDR 7 H SCALE CONTROL CADDR 7
C 9.0
13 TAP LOW PASS FILTER OR 25 TAP DECIMATION FILTER
ROUND CLIP (10-BITS)
C 9.0
12 TAP INTERPOLATION FILTER 128 PHASES
ROUND CLIP (10-BITS)
C 9.0
Figure 3-2: Horizontal Scaling Filter
YC
20
Y +10
RANGE ADJUST -512
Y 9.0
21 TAP LOW PASS FILTER OR 41 TAP DECIMATION FILTER
ROUND CLIP (11-BITS)
Y 10.0
24 TAP INTERPOLATION FILTER 128 PHASES
RANGE ADJUST +512
ROUND CLIP (10-BITS)
Y +10
20
YC
YADDR 7 V SCALE CONTROL CADDR 7
C 9.0
21 TAP LOW PASS FILTER OR 41 TAP DECIMATION FILTER
ROUND CLIP (10-BITS)
C 9.0
24 TAP INTERPOLATION FILTER 128 PHASES
ROUND CLIP (10-BITS)
C 9.0
Figure 3-3: Vertical Scaling Filter
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GF9320 Data Sheet
3.4.1 Scalar Processing
General 1D scaling is performed by cascading an FIR filter with an interpolation filter. The FIR filter is needed to band limit the input signal when the output Nyquist frequency is less than the input Nyquist frequency. The interpolation filter is used to resample the input signal to the new output rate. 3.4.1.1 FIR Filter The purpose of the FIR filters is to band limit or shape the input signal. Each filter is user programmable, with the coefficients derived depending on the required frequency response. The FIR filter can be used in one of two modes: decimate and non-decimate. Decimate mode can be used when the output rate is half the input rate. The advantage to using decimate mode is that the number of taps is approximately doubled by using two input clocks to compute one output sample. In non-decimate mode the filter is 21 taps (13 for horizontal colour difference due to the 4:2:2 input video structure). In decimate mode the filter is 41 taps (25 for horizontal colour difference). Vertically the same modes are available however due to the 4:2:2 sampling structure both luma and colour difference have equal numbers of taps, i.e. 41 taps for decimate and 21 taps for non-decimate. The filter operation is described by:
k = 10 HYT0_0 HY ( n ) + HYT 2k - 1_k [ HY I ( n - k ) + HY I ( n + k ) ] I k=1 HY O ( n ) 1024 = k = 10 HYT0_0 HY ( n ) + HYT 2k - 1_k [ HY I ( n - 2k + 1 ) + HY I ( n + 2k - 1 ) ] + I k=1 k = 10

H_FLT_DEC = 0
H_FLT_DEC = 1
k=1
HYT 2k [ HY I ( n - 2k ) + HY I ( n + 2k ) ]
k=6 HCT0_0 HC ( n ) + HCT 2k - 1_k [ HC I ( n - k ) + HC I ( n + k ) ] I k=1 HC O ( n ) 1024 = k = 10 HCT0_0 HC ( n ) + HCT 2k - 1_k [ HC I ( n - 2k + 1 ) + HC I ( n + 2k - 1 ) ] + I k=1 k=6
H_FLT_DEC = 0
H_FLT_DEC = 1
k=1
HCT 2k [ HC I ( n - 2k ) + HC I ( n + 2k ) ]
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GF9320 Data Sheet
k = 10 VYT0_0 VY ( n ) + VYT 2k - 1_k [ VY I ( n - k ) + VY I ( n + k ) ] I k=1 VY O ( n ) 1024 = k = 10 VYT0_0 VY ( n ) + VYT 2k - 1_k [ VY I ( n - 2k + 1 ) + VY I ( n + 2k - 1 ) ] + I k=1 k = 10

V_FLT_DEC = 0
V_FLT_DEC = 1
k=1
VYT 2k [ VY I ( n - 2k ) + VY I ( n + 2k ) ]
k = 10 VCT0_0 VC ( n ) + VCT 2k - 1_k [ VC I ( n - k ) + VC I ( n + k ) ] I k=1 VC O ( n ) 1024 = k = 10 VCT0_0 VC ( n ) + VCT 2k - 1_k [ VC I ( n - 2k + 1 ) + VC I ( n + 2k - 1 ) ] + I k=1 k = 10

V_FLT_DEC = 0
V_FLT_DEC = 1
k=1
VCT 2k [ VC I ( n - 2k ) + VC I ( n + 2k ) ]
where HYI(n), HCI(n), VYI(n) and VCI(n) are the FIR filter inputs, HYO(n), HCO(n), VYO(n) and VCO(n) are the FIR filter outputs, HYT, HCT, VYT, and VCT are the filter coefficients as given in Table 3-3: Horizontal Filter Coefficients and Table 3-4: Vertical Filter Coefficients, and 1024 is the DC gain of the filter. In non-decimate mode only one bank of coefficients are used (Bank 0), but in decimate mode both banks of coefficients are used (Bank 0 and Bank 1). 3.4.1.2 Interpolation Filter After FIR filtering the video data is passed to the interpolation filter where the rate conversion is performed. The interpolation filter is a polyphase filter that allows the output phase to be adjusted every clock cycle. The interpolation filter contains 128 phases (64 phases for horizontal colour difference). The phase selection allows generation of an output anywhere between two inputs with 1/128 input pixel resolution (1/64 for horizontal colour difference). The scaling control unit takes as input the scaling ratio (input / output), and starting phase (starting position of the first output pixel with respect to the input). With these parameters, the scaling control chooses the correct phasing sequence for the interpolator, determines which input samples should be held and for how long (up sampling), which interpolator outputs should be discarded (down sampling), and generates the new output.
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GF9320 Data Sheet
3.4.2 Resizing Parameters
In order to understand how to program the GF9320 to perform the necessary conversions an explanation of the window parameters, the zoom parameters and the filter parameters is necessary. 3.4.2.1 Window Parameters Figure 3-4: Input Window Definition - Progressive through Figure 3-7: Output Window Definition - Interlaced show how the GF9320 places a window over the input and output active video. This window is selected by using offsets from the active video area (HSTART, HSTOP, VSTART, VSTOP). Note that VSTART and VSTOP for interlaced video refers to field based offsets. The windowed portion is referred to as the live video and can cover the entire active video or just a portion of it. The size of the windowed portion is HLIVE by VLIVE pixels where: HLIVE = HSTOP - HSTART +1 VLIVE = VSTOP - VSTART +1 For interlaced video one field may have one more active line that the other. This means that VLIVE is longer for that field. Also, in interlaced film modes VSTART and VSTOP are still field-based offsets but VLIVE is frame based since the fields are merged and processed as a frame. The input video window is determined by IN_HSTART, IN_HSTOP, IN_VSTART, and IN_VSTOP. The size of the input windowed portion is IN_HLIVE by IN_VLIVE pixels. The output video window is determined by OUT_HSTART, OUT_HSTOP, OUT_VSTART, and OUT_VSTOP. The size of the output windowed portion is OUT_HLIVE by OUT_VLIVE pixels.
HLEN_TOT HLEN_ACT FRAME START VACT_POS
VLEN_TOT
ACTIVE VIDEO
VLEN_ACT
EAV
SAV VACT_POS >= 1 VLEN_TOT >= VACT_POS + VLEN_ACT + 1
Figure 3-4: Input Window Definition - Progressive
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GF9320 Data Sheet
HLEN_TOT HLEN_ACT FRAME START VACT_POS
Digital First Field F=0
VLEN_TOT \ 2 + 1
'\' Denotes integer division IF FLD_LONGER = 0
ACTIVE VIDEO (VLEN_ACT+1) \ 2 + 1
IF TOP_ACT_FLD = 0
VLEN_TOT \ 2 + 1
IF TOP_ACT_LONGER = 1 * AND TOP_ACT_FLD = 0
VACT_POS + VACT_DIF
0 +1 -1
IF (FLD_LONGER = TOP_ACT_FLD) IF (FLD_LONGER = 1) AND (TOP_ACT_FLD = 0) IF (FLD_LONGER = 0) AND (TOP_ACT_FLD = 1)
Digital Second Field F=1
VLEN_TOT \ 2 + 1
IF FLD_LONGER = 1
ACTIVE VIDEO IF TOP_ACT_LONGER = 1* AND TOP_ACT_FLD = 1
(VLEN_ACT +1)\ 2 + 1
EAV
SAV VACT_POS >= 1 VLEN_TOT >= 2*VACT_POS + VLEN_ACT + 1
* - VLEN_ACT even implies TOP_ACT_LONGER = 1
Figure 3-5: Input Window Definition - Interlaced
HLEN_TOT HLEN_ACT
VSTART
ACTIVE VIDEO
VLEN_TOT
VSTOP
LIVE VIDEO
VLEN_ACT+1
HSTOP HSTART 0 <= HSTART < HSTOP <= HLEN_ACT 0 <= VSTART < VSTOP <= VLEN_ACT
Figure 3-6: Output Window Definition - Progressive
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GF9320 Data Sheet
HLEN_TOT HLEN_ACT
VSTART Digital First Field (F=0)
ACTIVE VIDEO
VLEN_TOT \ 2 + 1
'\' Denotes integer division IF FLD_LONGER = 0
IF TOP_ACT_LONGER = 1* AND TOP_ACT_FLD=0
VSTOP + 1
LIVE VIDEO (VLEN_ACT+1) \ 2 + 1
IF TOP_ACT_LONGER = 1* AND TOP_ACT_FLD = 0
VSTART Digital Second Field (F=1)
ACTIVE VIDEO VLEN_TOT \ 2 + 1 LIVE VIDEO IF TOP_ACT_LONGER = 1* AND TOP_ACT_FLD = 1 IF FLD_LONGER = 1
IF TOP_ACT_LONGER = 1* AND TOP_ACT_FLD=1
VSTOP + 1
(VLEN_ACT+1) \ 2 + 1
HSTOP * - VLEN_ACT even implies TOP_ACT_LONGER = 1 0 <= HSTART < HSTOP <= HLEN_ACT 0 <= VSTART < VSTOP <= (VLEN_ACT+1) \ 2
HSTART
Figure 3-7: Output Window Definition - Interlaced
3.4.2.2 FIR Filter Parameters The FIR filter shape is programmable by downloading the filter coefficients. The horizontal filter coefficients and download positions are given in Table 3-3: Horizontal Filter Coefficients. The vertical filter coefficients are given in Table 3-4: Vertical Filter Coefficients. The overall gain of the FIR filter is 1024, but the range of coefficients is larger to permit implementation of enhancement filters. Note that the coefficients change meaning depending on the filter structure (i.e. if the filter is in decimate mode or not). The filter structure is determined by the FLT_DEC parameter. If H_FLT_DEC is 1, then the horizontal FIR filter is configured in decimate mode. If H_FLT_DEC is 0, then the horizontal FIR filter is configured in non-decimate mode. If V_FLT_DEC is 1, then the vertical FIR filter is configured in decimate mode. If V_FLT_DEC is 0, then the vertical FIR filter is configured in nondecimate mode.
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GF9320 Data Sheet
Table 3-3: Horizontal Filter Coefficients Parameter
twelve_zeros HYT2 HYT4 HYT6 HYT8 HYT10 HYT12 HYT14 HYT16 HYT18 HYT20 HYT0_0 HYT1_1 HYT3_2 HYT5_3 HYT7_4 HYT9_5 HYT11_6 HYT13_7 HYT15_8 HYT17_9 HYT19_10 twelve_zeros HCT2 HCT4 HCT6 HCT8 HCT10 HCT12 HCT0_0 HCT1_1 HCT3_2
No. of Bits
12 12 11 10 10 9 9 9 9 8 8 12 12 11 10 10 9 9 9 9 8 8 12 11 9 9 8 8 8 12 11 9
Range
[0, 0] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [0, 0] [-1024, 1023] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-128, 127] [-2048, 2047] [-1024, 1023] [-256, 255]
Word Position
HF[343:332] HF[331:320] HF[319:309] HF[308:299] HF[298:289] HF[288:280] HF[279:271] HF[270:262] HF[261:253] HF[252:245] HF[244:237] HF[236:225] HF[224:213] HF[212:202] HF[201:192] HF[191:182] HF[181:173] HF[172:164] HF[163:155] HF[154:146] HF[145:138] HF[137:130] HF[129:118] HF[117:107] HF[106:98] HF[97:89] HF[88:81] HF[80:73] HF[72:65] HF[64:53] HF[52:42] HF[41:33]
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GF9320 Data Sheet
Table 3-3: Horizontal Filter Coefficients (Continued) Parameter
HCT5_3 HCT7_4 HCT9_5 HCT11_6
No. of Bits
9 8 8 8
Range
[-256, 255] [-128, 127] [-128, 127] [-128, 127]
Word Position
HF[32:24] HF[23:16] HF[15:8] HF[7:0]
Table 3-4: Vertical Filter Coefficients Parameter
twelve_zeros VYT2 VYT4 VYT6 VYT8 VYT10 VYT12 VYT14 VYT16 VYT18 VYT20 VYT0_0 VYT1_1 VYT3_2 VYT5_3 VYT7_4 VYT9_5 VYT11_6 VYT13_7 VYT15_8 VYT17_9 VYT19_10 twelve_zeros VCT2 VCT4
No. of Bits
12 12 11 10 10 9 9 9 9 8 8 12 12 11 10 10 9 9 9 9 8 8 12 12 11
Range
[0, 0] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [0, 0] [-2048, 2047] [-1024, 1023]
Word Position
VF[431:420] VF[419:408] VF[407:397] VF[396:387] VF[386:377] VF[376:368] VF[367:359] VF[358:350] VF[349:341] VF[340:333] VF[332:325] VF[324:313] VF[312:301] VF[300:290] VF[289:280] VF[279:270] VF[269:261] VF[260:252] VF[251:243] VF[242:234] VF[233:226] VF[225:218] VF[217:206] VF[205:194] VF[193:183]
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GF9320 Data Sheet
Table 3-4: Vertical Filter Coefficients (Continued) Parameter
VCT6 VCT8 VCT10 VCT12 VCT14 VCT16 VCT18 VCT20 VCT0_0 VCT1_1 VCT3_2 VCT5_3 VCT7_4 VCT9_5 VCT11_6 VCT13_7 VCT15_8 VCT17_9 VCT19_10 fill
No. of Bits
10 10 9 9 9 9 8 8 12 12 11 10 10 9 9 9 9 8 8 4
Range
[-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [0, 0]
Word Position
VF[182:173] VF[172:163] VF[162:154] VF[153:145] VF[144:136] VF[135:127] VF[126:119] VF[118:111] VF[110:99] VF[98:87] VF[86:76] VF[75:66] VF[65:56] VF[55:47] VF[46:38] VF[37:29] VF[28:20] VF[19:12] VF[11:4] VF[3:0]
3.4.2.3 Zoom Parameters The zoom parameters (IN_HSTART_PHASE, IN_VSTART_PHASE, H_ZOOM_RATIO, and V_ZOOM_RATIO) specify the precise conversion from the input live video to the output live video. IN_HSTART_PHASE and IN_VSTART_PHASE allows for starting the interpolator with sub-pixel accuracy. This allows for maintaining the true center of picture when zooming and panning. The zoom ratio is approximately:
IN_HLIVE 524288 ------------------------------------------------ OUT_VLIVE H_ZOOM_RATIO = IN_HLIVE 524288 ------------------------------------------------ OUT_HLIVE 2 IN_VLIVE 524288 ------------------------------------------------ OUT_VLIVE V_ZOOM_RATIO = IN_VLIVE 524288 ------------------------------------------------ OUT_VLIVE 2
H_FLT_DEC = 0 H_FLT_DEC = 1 V_FLT_DEC = 0 V_FLT_DEC = 1
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GF9320 Data Sheet The above equations hold only approximately because the zoom ratio must be adjusted to maintain the true center of picture. When using the GF9320 there is a preventable condition whereby certain memory configurations cause artifacts in the output image. It is dependent upon the vertical parameters of the output video and the number of SDRAMS employed in the right memory bank as follows: OUT_VLIVE modulo (64 * N) = (64 * N) - 3 or (64 * N) - 1 Where N is the number of memories in each array of the right bank, MEM_CONFIG_RIGHT, and OUT_VLIVE = OUT_VSTOP - OUT_VSTART + 1 Artifacts can be avoided by monitoring for the condition. When detected, add or subtract one (1) from the OUT_VSTOP value while maintaining the condition: 0 <= OUT_VSTART < OUT_VSTOP Note that both fields must be checked for this condition when the output is interlaced with one field longer.
3.4.3 Dynamic Zoom and Pan Considerations
The GF9320 is designed to perform frame accurate zooming and panning. Some of the downloaded zoom and pan parameters are used by multiple blocks within the GF9320. These blocks operate on the video data at different time frames. For instance, the input control block operates on the video data on frame / field (N) while the vertical scaling block operates on the video data on frame / field (N-1). Both these blocks need the IN_VSTART parameter. So, the IN_VSTART parameter must be used by the scaling block one field / frame later than the input block. Registering the IN_VSTART parameter on the field / frame boundary before the scaling block uses it does this. While most dynamic zoom and pan situations are taken care of automatically by the GF9320, some dynamic zoom and pan conditions require special downloading. 3.4.3.1 H_PROC_FIRST Switching The H_PROC_FIRST download bit is special because it actually changes the configuration of the GF9320. In particular, changing the H_PROC_FIRST bit from 1 to 0 makes the horizontal filter switch from operating on field / frame (N) to operating on field / frame (N-2) and vice versa. Note that changing the H_PROC_FIRST bit from 1 to 0 is changing from down sampling to up sampling. In order to handle this special case smoothly, a 1:1 horizontal zoom factor must be downloaded.
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GF9320 Data Sheet The recommended sequence for switching from H_PROC_FIRST equal to 1 to 0 (i.e. down sampling to up sampling) is: 1. Keep H_PROC_FIRST equal to 1 and download H_ZOOM_RATIO equal to 524,288 (down sampling). 2. Wait at least 2 frames / fields. 3. Change H_PROC_FIRST to 0 and download H_ZOOM_RATIO equal to 524,287 (up sampling). 4. Change to the desired H_ZOOM_RATIO. The recommended sequence for switching from H_PROC_FIRST equal to 0 to 1 (i.e. up sampling to down sampling) is: 1. Keep H_PROC_FIRST equal to 0 and download a H_ZOOM_RATIO equal to 524,287 (up sampling). 2. Change H_PROC_FIRST to 1 and download H_ZOOM_RATIO equal to 524,288 (down sampling). 3. Change to the desired H_ZOOM_RATIO. 3.4.3.2 V_FLT_DEC Switching The vertical filter operates on field / frame (N-1), but the vertical filter coefficients operate on field / frame (N). When the V_FLT_DEC is switched from 0 to 1 or vice versa, the vertical filter coefficients must be delayed by one field / frame so that they operate on the same time frame. This is necessary because the filter coefficients are used differently in decimation mode and a non-decimation filter would be used in decimation mode and vice versa. This would most directly affect the DC gain of the filter that may be perceived as a brightness change in the output video. The horizontal coefficients do not need to be delayed when switching H_FLT_DEC because the horizontal filter and the horizontal coefficients operate on the same frame / field (N). Even though H_FLT_DEC is switched, down sampling (H_PROC_FIRST=1) is indicated. Delaying the vertical filter coefficients may not be necessary depending on the application. 3.4.3.3 Pseudo Synchronous Film Mode Conversions This section applies to any film mode conversion when the input frame rate or the output film rate is 3:2 pull-down, but the input rate is not (i.e. 48 60, 24 60). In these cases the zoom and pan update rate is restricted to every other film frame as shown in Figure 3-8: 24/24/60 Download Restrictions and Figure 3-9: 48/24/60 Download Restrictions. This is because the output circuit must be updated on an output field / frame boundary.
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GF9320 Data Sheet
IN_FILM_RATE=2 OUT_FILM_RATE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR
VIDEO SEQUENCE
0 D
1 A
2 B
3 C
VERTICAL PROCESSING:
OE_AB
VIDEO SEQUENCE OE_CD
3
0
1
2
3
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE
2
2 B
2
3 C
3
0
0 D
0
1 A
1
2
Do not download in the shaded regions (OE_AB=1). If the GF9320 is downloaded in the shaded region, the output circuit will be updated in the middle of an output field/frame and will cause one field/ frame of the output to be invalid.
Figure 3-8: 24/24/60 Download Restrictions
IN_FILM_RATE=1
OUT_FILM_RATE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
0 B
1
2 C
3
4 D
5
6 A
7
0
VERTICAL PROCESSING:
OE_AB VIDEO SEQUENCE OE_CD
6
0
2
4
6+7
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
4
4 D
4
6 A
6
0
0 B
0
2 C
2
4
Do not download in the shaded regions (OE_AB=1). If the GF9320 is downloaded in the shaded region, the output circuit will be updated in the middle of an output field/frame and will cause one field/ frame of the output to be invalid.
Figure 3-9: 48/24/60 Download Restrictions
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GF9320 Data Sheet
3.5 SDRAM Memory Interface
3.5.1 Memory Interface Description
To achieve high quality scaling of images in two dimensions, separate processing has to be done in the horizontal and vertical dimensions using one dimensional filter banks. Hence, the input image has to be transposed before and after vertical processing and uses SDRAMs to achieve real-time transposition of digital video images using high quality filters. The SDRAM controller within the GF9320 acts as the master controller of the memory arrays. To perform a transpose operation the memory controller writes the entire image from one field into the image buffer and then reads it out during the next field. Further, during film mode processing, the controller can put two consecutive image fields together and read them out in the next frame as a single progressive frame. The latter technique is used for processing film material with 3:2 pull-down. We can also separate even and odd fields from a progressive frame to create film material with 3:2 pull-down. The memory organization for transposing images at high data rates is shown in Figure 3-10: Memory Interface.
DATA[19:0]
DATA_A[19:0]
DATA_C[19:0]
DATA[19:0]
ADDR[10:0] BA
ADDR_A[10:0] BA_A CK_A CKEN_A RAS_A CAS_A WE_A CS_A[3:0] DATAEN_AB
ADDR_C[10:0] BA_C CK_C CKEN_C RAS_C CAS_C WE_C CS_C[3:0] DATAEN_CD
ADDR[10:0] BA CLK CLKEN RAS CAS WE CS[3:0] DATAEN
MEMORY ARRAY A
CLK CLKEN RAS CAS WE CS[3:0] DATAEN
MEMORY ARRAY C
GF9320
DATA[19:0]
DATA_B[19:0]
DATA_D[19:0]
DATA[19:0]
ADDR[10:0] BA
ADDR_B[10:0] BA_B CK_B CKEN_B RAS_B CAS_B WE_B CS_B[3:0]
DATAEN_AB
ADDR_D[10:0] BA_D CK_D CKEN_D RAS_D CAS_D WE_D CS_D[3:0]
DATAEN_CD
ADDR[10:0] BA CLK CLKEN RAS CAS WE CS[3:0] DATAEN
MEMORY ARRAY B
CLK CLKEN RAS CAS WE CS[3:0] DATAEN
MEMORY ARRAY D
Figure 3-10: Memory Interface
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GF9320 Data Sheet The memory organization consists of four arrays of memories communicating with the GF9320. Each array can contain anywhere between one to five SDRAMs based on format conversion mode. Memory array A and B compose the left bank while memory array C and D compose the right bank. To achieve high bandwidth, the memory arrays are arranged in an interleaved fashion. That is, when one field in written into memory array A, the other field will be read out of memory array B. The sequence of read / write operations that takes place in non-film applications is shown in Figure 3-11: Timing Diagram of Data between GF9320 and SDRAMs for non-film Modes.
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
MEMORY ARRAY A
WRITE FIELD1
READ FIELD1
WRITE FIELD3
READ FIELD3
WRITE FIELD5
MEMORY ARRAY B
WRITE FIELD2
READ FIELD2
WRITE FIELD4
READ FIELD4
MEMORY ARRAY C
WRITE FIELD1
READ FIELD1
WRITE FIELD3
READ FIELD3
MEMORY ARRAY D
WRITE FIELD2
READ FIELD2
WRITE FIELD4
Figure 3-11: Timing Diagram of Data between GF9320 and SDRAMs for nonfilm Modes
The data from an odd field is written into memory array A during Field3. At the same time data from the previous (even) field will be read out as a transposed image from memory array B. The horizontal rows of data read out from memory array B will then be processed (vertical processing) within the GF9320 and written into memory array D. Simultaneously, the vertically processed image data from two fields back which was written into memory array C will be read out. When the image is read out from memory array C, it went through another image transposition so that the image is back to its original orientation. Effectively, there is a two field / frame delay when processing non-film material. The GF9320 experiences significantly more processing time in the vertical processing section due to the bandwidth limitations of the SDRAMs. For some conversions the processing time might exceed the available time. This condition can be circumvented by either increasing the number of memories in the array or by increasing the processing clock rate. During vertical processing, the GF9320 pre-reads (number of pixels = PIX2READ) into its internal FIFO, before the beginning of every scan line so that it can supply the pixels from the FIFO into the one-dimensional filter in an uninterrupted way. The number of pixels to be pre-read is chosen based on several I/O parameters so that it is high enough to supply data continuously to the filter but low enough to complete the vertical processing in the available time.
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GF9320 Data Sheet The PIX2READ parameter is calculated by:
IN_VLEN_ACT --------------------------------------------------------2 - IN_PROGRESSIVE PIX2READ = MIN {MAX (8 + CEIL ---------------------------------------------------------------------------------- ,10), 127} 64 x ( 4 - MEM_CONFIG_LEFT )
Where IN_VLEN_ACT is the total number of active lines per frame, CEIL(x) is the smallest integer larger than x;
a MAX (a,b) = b a MAX (a,b) = b if a b if a < b if a b if a < b
80Mbits or 5 x 16Mbit SDRAMs are required to store 2048 x 2048 x 20 bits (maximum image size). As illustrated in Figure 3-12: Architecture of Memory Array with four 1Mx16 and one 4Mx4 SDRAMs, the memory array has a 20-bit data bus path, supported by blocks of four 1Mx16 SDRAMs and one 4Mx4 used in parallel, sharing a common address / control bus. 1Mx16 SDRAMs store the upper significant bits of luminance Y[10:2] and colour difference C[10:2]. 4Mx4 SDRAM stores the lower significant bits Y[1:0] and C[1:0].
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] BA CLK CLKEN RAS CAS WE CS0 DATAEN A[10:0] BA CLK CKE RAS CAS WE CS DQM CS1 SDRAM0 1Mx16 DATA[19:4] DQ[15:0] A[10:0] BA CLK CKE RAS CAS WE CS DQM CS2 SDRAM1 1Mx16 DATA[19:4] DQ[15:0] A[10:0] BA CLK CKE RAS CAS WE CS DQM CS3 SDRAM2 1Mx16 DATA[19:4] DQ[15:0] A[10:0] BA CLK CKE RAS CAS WE CS DQM SDRAM3 1Mx16 DATA[3:0] DQ[15:0] A[10:0] BA CLK CKE RAS CAS WE CS DQM SDRAM(LSB) 4Mx4
CS[3:0]
Figure 3-12: Architecture of Memory Array with four 1Mx16 and one 4Mx4 SDRAMs
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GF9320 Data Sheet All elements in the array can be simultaneously selected for command execution by activating the chip select signals or commands can be directed to a particular element in the array by activating the chip select signal for that element and deactivating the chip select signal for the others. Figure 3-13: Memory Array Architecture with Four 4MX16 and One 16MX4 SDRAMs shows the pin connections (and slightly different addressing requirements) needed for more common 64M SDRAMs within a memory array. The number of memories for a given format conversion remains the same independent of memory (16M or 64M) being used.
DATA[19:0] DATA[19:4] DQ[15:0] BA ADDR[10:0] CLK CLKEN RAS CAS WE CS0 DATAEN BA[0] A[10:0] CLK CKE RAS CAS WE CS DQM A[11] BA[1] CS[3:0] CS1 SDRAM0 4Mx16 DATA[19:4] DQ[15:0] BA[0] A[10:0] CLK CKE RAS CAS WE CS DQM A[11] BA[1] CS2 SDRAM1 4Mx16 DATA[19:4] DQ[15:0] BA[0] A[10:0] CLK CKE RAS CAS WE CS DQM A[11] BA[1] CS3 SDRAM2 4Mx16 DATA[19:4] DQ[15:0] BA[0] A[10:0] CLK CKE RAS CAS WE CS DQM A[11] BA[1] SDRAM3 4Mx16 DATA[3:0] DQ[3:0] BA[0] A[10:0] CLK CKE RAS CAS WE CS DQM A[11] BA[1] SDRAM(LSB) 16Mx4
Figure 3-13: Memory Array Architecture with Four 4MX16 and One 16MX4 SDRAMs
To reduce system cost, the memory array architecture is made scalable. That is, when transposing smaller image sizes or when processing 8-bit images, a lesser number of SDRAMs per memory array are required. Table 3-5: Minimum SDRAM Configurations for Mode 8 (default mode) shows the memory requirements for various format conversions.
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GF9320 Data Sheet
Table 3-5: Minimum SDRAM Configurations for Mode 8 (default mode) Image Width (max) x max (Input Image Height, Output Image Height)a
2048 x 2048 2048 x 1536 2048 x 1024 2048 x 512
Number of SDRAMs required / ARRAY [Y, C] 10-bits
4 (1Mx16) and 1 (4Mx4) 3 (1Mx16) and 1 (4Mx4) 2 (1Mx16) and 1 (4Mx4) 1 (1Mx16) and 1 (4Mx4)
Download Parameters
[Y, C] 8-bits
4 (1Mx16) 3 (1Mx16) 2 (1Mx16) 1 (1Mx16)
MDLb
0 0 0 0
MCLc
00 01 10 11
MDRd
0 0 0 0
MCRe
00 01 10 11
a. max(a, b) = a when a >= b, else b when a < b. b.MDL stands for the parameter MODE_16_LEFT. c.MCL stands for the parameter MEM_CONFIG_LEFT. d.MDR stands for the parameter MODE_16_RIGHT. e.MCR stands for the parameter MEM_CONFIG_RIGHT.
Figure 3-14: Architecture of Memory Array with Lesser Number of SDRAMs per Array shows the memory array architecture when the number of memories is reduced to 2 SDRAMS and one SDRAM (8 bit processing) per memory array.
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] BA CLK CLKEN RAS CAS WE CS0 DATAEN A[10:0] BA CLK CKE RAS CAS WE CS DQM SDRAM0 1Mx16 DATA[3:0] DQ[15:0] A[10:0] BA CLK CKE RAS CAS WE CS DQM SDRAM(LSB) 4Mx4
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] BA CLK CLKEN RAS CAS WE CS0 DATAEN CS[3:0] A[10:0] BA CLK CKE RAS CAS WE CS DQM SDRAM0 1Mx16 DATA[3:0]
CS[3:0]
a) Two SDRAMs per Array; one for MSB and one for LSB
b) One SDRAMs per Array, one for 8 bit proccessing -- LSB are pulled down with 1K resistor to ground
Figure 3-14: Architecture of Memory Array with Lesser Number of SDRAMs per Array
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GF9320 Data Sheet
3.5.2 SDRAM Specifications
The speed grade of the SDRAM is chosen depending on the processing clock frequency. For example, if the processing clock is running at 74.25MHz, SDRAM with a speed grade of -10 or 100MHz should be selected.
3.5.3 Special Processing
3.5.3.1 Model 16 To further decrease the memory requirements at the expense of processing time an additional mode is available. Table 3-6: Minimum SDRAM Configurations for Mode 16 summarizes the memory requirements for various format conversions in this mode.
Table 3-6: Minimum SDRAM Configurations for Mode 16 Image Width (max) x max (Input Image Height, Output Image Height)a
1024 x 2048 1024 x 1024
Number of SDRAMs required / ARRAY [Y, C] 10-bits
2 (1Mx16) and 1 (4Mx4) 1 (1Mx16) and 1 (4Mx4)
Download Parameters
[Y, C] 8-bits
2 (1Mx16) 1 (1Mx16)
MDLb
1 1
MCLc
10 11
MDRd
1 1
MCRe
10 11
a.max (a, b) = a when a >= b, else b when a < b. b.MDL stands for the parameter MODE_16_LEFT. c.MCL stands for the parameter MEM_CONFIG_LEFT. d.MDR stands for the parameter MODE_16_RIGHT. e.MCR stands for the parameter MEM_CONFIG_RIGHT.
3.5.4 Film Processing
During film processing the GF9320 uses the external signals FILM_FR and OUT_FRST to encode or decode the 3:2 pull-down sequence. The timing of these signals for different modes (film and non-film) is shown in Figure 3-15: 60/60/60 Processing through Figure 3-40: 24p/24p/48p Processing. When the input video is from a film material with 3:2 pull-down, the GF9320 processes the image vertically after combining the even and odd fields to achieve better quality resizing. Duplicate fields in the input sequence are rejected by not writing into the memory. Note that in film modes memory switching does not occur at every field / frame boundary. It depends on the input and output film formats. For example, when the input is video with 3:2 pull-down, the left array of memories switch only after even and odd fields have been put together. The switching point is shown in the timing diagram by DATAEN_AB and DATAEN_CD signals that are, respectively, the output enable signals for left and right arrays. The GF9320 achieves 3:2 pull-down at the output by separately reading out the even and odd fields.
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GF9320 Data Sheet The film sequences shown in Figure 3-15: 60/60/60 Processing through Figure 340: 24p/24p/48p Processing are not the only film frame sequences that the GF9320 can generate. Note that an X through an input video sequence through Figure 3-16: 30i/24p/24i Processing to Figure 3-34: 48p/24p/24p Processing denotes a discarded frame when performing 3:2 pulldown compensation. Other input / output film sequences are possible. The input control uses the rising edge of FILM_FR to set the input film sequence and the film frame reset sent to the output controller. The first TRS V-bit after the rising edge of FILM_FR marks the beginning of a 3:2 (starting with 3) or 2:2 film sequences.
IN_FILM_RATE=3 OUT_FILM_RATE=3
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE
A1
B1
A2
B2
A3
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE
A1
B1
A2
B2
DATAEN_CD VIDEO SEQUENCE
A1
B1
A2
B2
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE
A1
B1
A2
Figure 3-15: 60/60/60 Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
AE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
AO + AE
BO + BE
CO + CE
DO + DE
AO + AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
DO
DE
AO
AE
BO
BE
CO
CE
DO
D
A
B
C
Figure 3-16: 30i/24p/24i Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
A
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
D
A
B
C
D
A
B
C
Figure 3-17: 60p/24p/24p Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
AE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
AO + AE
BO + BE
C O + CE
D O + DE
AO + AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
D O + DE
AO + AE
BO + BE
C O + CE
D
A
B
C
Figure 3-18: 30i/24p/24p Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
A
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE **FILM SEQUENCE
CE
DO
DE
DO
AE
AO
BE
BO
BE
CO
CE
DO
B C ** Film sequence is not maintained in the output.
D
A
Figure 3-19: 60p/24p/30i Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_REF=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
A
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
CO
DE
DO
DE
AO
AE
BO
BE
BO
CE
CO
DE
D
A
B
C
*** Film sequence at the output is same as the input. (OUT_REF = 1)
Figure 3-20: 60p/24p/30i (OUT_REF=1) Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
AE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
AO + AE
BO + BE
C O + CE
D O + DE
AO + AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE **FILM SEQUENCE
CE
DO
DE
DO
AE
AO
BE
BO
BE
CO
CE
DO
B ** Film sequence is not maintained in the output.
C
D
A
Figure 3-21: 30i/24p/30i Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_REF=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
AE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
AO + AE
BO + BE
C O + CE
D O + DE
AO + AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
CO
DE
DO
DE
AO
AE
BO
BE
BO
CE
CO
DE
D
A
B
C
***Film sequence at the output is same as the input. (OUT_REF= 1)
Figure 3-22: 30i/24p/30i (OUT_REF=1) Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=1 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
AE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
AO + AE
BO + BE
C O + CE
D O + DE
AO + AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
DO+DE
D O+DE
AO+AE
AO+AE
BO+BE
BO+BE
C O+CE
CO+CE
DO+DE
D
A
B
C
Figure 3-23: 30i/24p/48p Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
A
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
D
D
A
A
B
B
C
C
B
D
A
B
C
Figure 3-24: 60p/24p/48p Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
A
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE
A
B
C
D
A
DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
DO
DE
AO
AE
BO
BE
CO
CE
DO
D
A
B
C
Figure 3-25: 60p/24p/24i Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
A
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
C
D
D
D
A
A
B
B
B
C
C
D
D
A
B
C
Figure 3-26: 60p/24p/60p Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
AE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
AO + AE
BO + BE
CO + CE
D O + DE
AO + AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
CO +CE DO +D E
DO +D E DO+D E AO +AE AO +AE
BO +BE BO+BE BO+BE CO +CE
CO +CE D O+D E
D
A
B
C
Figure 3-27: 30i/24p/60p Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
DO
DE
AO
AE
BO
BE
CO
CE
DO
D
A
B
C
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
C O+CE
D O+DE
AO+AE
BO+BE
C O+CE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
Figure 3-28: 24i/24p/30i Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
D
D
A
A
B
B
C
C
D
D
A
B
C
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
C
D
A
B
C
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
Figure 3-29: 48p/24p/30i Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
B
B
C
C
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
D
D
D
A
A
B
B
B
C
C
D
D
A
B
C
Figure 3-30: 48p/24p/60p Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
BO
BE
CO
CE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE
AO+AE
BO+BE
C O+CE
D O+DE
AO+AE
DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
D O+DE DO+D E DO+D E AO+AE AO+AE BO+BE BO+BE BO+BE C O+CE CO+C E D O+DE
D
A
B
C
Figure 3-31: 24i/24p/60p Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=0
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR
VIDEO SEQUENCE FILM SEQUENCE
BO
BE
CO
CE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
AO+AE
BO+BE
C O+CE
D O+DE
AO+AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
DO
DE
AO
AE
BO
BE
CO
CE
DE
D
A
B
C
Figure 3-32: 24i/24p/24i Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
B
B
C
C
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
DO
DE
AO
AE
BO
BE
CO
CE
DO
D
A
B
C
Figure 3-33: 48p/24p/24i Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
B
B
C
C
D
D
A
A
B
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
D
A
B
C
D
A
B
C
Figure 3-34: 48p/24p/24p Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
BO
BE
CO
CE
DO
DE
AO
AE
BO
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
AO+AE
BO+BE
C O+CE
D O+DE
AO+AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
D O+DE
AO+AE
BO+BE
C O+C E
D
A
B
C
Figure 3-35: 24i/24p/24p Processing
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GF9320 Data Sheet
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
D
A
B
C
D
A
B
C
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
C
D
A
B
C
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
BO
BE
BO
CE
CO
DE
DO
DE
AO
AE
BO
B
C
D
A
Figure 3-36: 24p/24p/30i Processing
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
B
C
D
A
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE
A
B
C
D
A
DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
DO
DE
AO
AE
BO
BE
CO
CE
DO
D
A
B
C
Figure 3-37: 24p/24p/24i Processing
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GF9320 Data Sheet
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
B
C
D
A
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
D
A
B
C
D
A
B
C
Figure 3-38: 24p/24p/24p Processing
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
D
A
B
C
D
A
B
C
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
C
D
A
B
C
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
B
B
B
C
C
D
D
D
A
A
B
B
C
D
A
Figure 3-39: 24p/24p/60p Processing
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GF9320 Data Sheet
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
B
C
D
A
B
C
D
A
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
A
B
C
D
A
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
D
D
A
A
B
B
C
C
D
D
A
B
C
Figure 3-40: 24p/24p/48p Processing
During film processing there is a possibility that for some conversions the GF9320 could violate the refresh period (64 ms) of the SDRAM. If a violation is found (IN_REFR_LEFT or OUT_REFR_RIGHT = '1'), then the appropriate (left / right) refresh bit should be activated in the download stream of parameters to the GF9320. Alternatively, Table 3-7: Input and Output Formats Requiring Refresh can be used to determine which input and output formats require refresh bits to be active.
Table 3-7: Input and Output Formats Requiring Refresh Input Format IN_REFR_LEFT=1
24p/25p 48p/50p 30i/60p with 3:2 pull-down
Output Format OUT_REFR_RIGHT=1
24p/25p
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GF9320 Data Sheet
3.5.5 Processing Delay
Processing delay for video through the GF9320 depends on the conversion. Table 3-8: Processing Delay for Various Conversions shows the processing delay for different film and non-film modes.
Table 3-8: Processing Delay for Various Conversions Conversion Delay (Input Frames / Fields)
[frame / field modes - 60Hz V processing]
Note: All other frame rates are identical with appropriate time scaling 30i 30i 60p 60p 30i 60p 30i 60p 1/30 seconds (2 fields) 1/30 seconds (2 fields) 1/30 seconds (2 frames) 1/30 seconds (2 frames)
[2:2 modes - 30Hz V processing]
30i 60p 30p 30p 30i 30i 30p 30p 30i 60p 30i 60p 1/15 seconds (4 fields) 1/15 seconds (4 frames) 1/15 seconds (2 frames) 1/15 seconds (2 frames) 1/15 seconds (4 fields) 1/15 seconds (4 fields)
[3:2 modes - 24Hz V processing]
30i 30i 30i 30i 60p 60p 24i 24i 24p 24p 30i 60p 24p 24i 24p 24i 30i 60p 30i 60p 1/10-1/12 seconds (5-6 fields) 1/10-1/12 seconds (5-6 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (3.6-4 fields) 3/40-1/12 seconds (3.6-4 fields) 3/40-1/12 seconds (1.8-2 frames) 3/40-1/12 seconds (1.8-2 frames)
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GF9320 Data Sheet
3.5.6 Pin Descriptions
The GF9320 uses the transpose memory bus interface signals to communicate with external memory (SDRAMs). The GF9320 is the master device on the bus interface and it controls the timing of the address and data flow. Each signal in the bus interface is described as follows: 3.5.6.1 Address Bus ADDR_A[10:0], ADDR_B[10:0], ADDR_C[10:0], ADDR_D[10:0] The address bus is shared by all the memories in the array. The address bus bit BA_A (Bank Select) selects which bank is to be active in memory array. BA_A low selects bank A and BA_A high selects bank B within the memory. During a bank activate command cycle, ADDR_A[10:0] defines the row address when sampled at the rising clock edge. During a read / write cycle, ADDR_A[9:0] defines the column address when sampled at the rising clock edge. In addition to the column address ADDR_A10 is used to invoke auto-precharge operation. Similarly, ADDR_B[10:0], ADDR_C[10:0], ADDR_D[10:0] form the address bus of memory arrays B, C and D respectively. 3.5.6.2 Data Bus DATA_A[19:0], DATA_B[19:0], DATA_C[19:0], DATA_D[19:0] The data bus is bi-directional. Valid data is driven on the data bus by the GF9320 during write cycle, which is accepted back by the GF9320 during the read cycles. These cycles involve transfers of bursts of data between the SDRAM core and registers of GF9320. Luminance data Y[9:2] are available on DATA_A/B/C/ D[19:12] while least significant bits Y[1:0] are available on DATA_A/B/C/D[3:2]. Colour difference data C[9:2] are available on DATA_A/B/C/D[11:4] while least significant bits C[1:0] are available on DATA_A/B/C/D[1:0]. 3.5.6.3 Command Bus [RAS_A, CAS_A, WE_A], [RAS_B, CAS_B, WE_B], [RAS_C, CAS_C, WE_C], [RAS_D, CAS_D, WE_D] These bus signals are asserted by the GF9320 when commands have to be executed on the SDRAM memory array A. Similarly, [RAS_B, CAS_B, WE_B], [RAS_C, CAS_C, WE_C] and [RAS_D, CAS_D, WE_D] are asserted to execute commands on memory array B, C and D respectively. These signals are considered valid only if the respective CS pin is low during the active edge of the clock.
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GF9320 Data Sheet CKEN_A, CKEN_B, CKEN_C, CKEN_D CKEN_A, CKEN_B, CKEN_C and CKEN_D are used to drive memory arrays A, B, C and D respectively. CKEN input suspends data (i.e. read data remains valid and write data is inhibited) during an active read or write. The GF9320 activates CKEN_A and CKEN_B signals during field / frame write cycle to drop pixels. CKEN_C and CKEN_D are activated during field / frame read cycle to hold pixel values. These signals are considered valid only if the respective CS pin is low during the active edge of the clock. CS_A[3:0], CS_B[3:0], CS_C[3:0], CS_D[3:0] The CS_A[3:0] signals from the GF9320 allows selection of individual or multiple SDRAMs within the memory array A. The appropriate SDRAM(s) is selected when the respective CS_A[3:0] pin is active low on the rising edge of clock. CS_B[3:0], CS_C[3:0] and CS_D[3:0] select SDRAMs within memory arrays B, C and D respectively. DATAEN_AB, DATAEN_CD These signals are driven by the GF9320 only during start-up to prevent data contention. When sampled high, it places the data bus buffers within the SDRAM in a high impedance state. After successful initialization, DATAEN_AB and DATAEN_CD stay low until the next power-up reset. DATAEN_AB is shared by memories in banks A and B, while DATAEN_CD is shared by memories in banks C and D. CK_A, CK_B, CK_C, CK_D CK_A, CK_B, CK_C and CK_D are clock signals, which drive the SDRAMs clock pins in memory array A, B, C and D respectively.
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GF9320 Data Sheet
3.6 Output Processor
A block diagram of the output processor is shown in Figure 3-41: Output Processor Block Diagram. The output processor consists of three major functions: 1. Colour difference over-sample 2. Matrix conversion 3. Output format The colour difference over-sample function is necessary for colour matrix conversion and to provide a 4:4:4 output. The colour difference over-sample block also performs colour background insertion and horizontal edge shaping. Horizontal edge shaping is done to eliminate overshoot on edges when the scaled output does not fill the entire output raster. That is, when OUT_HSTART is greater that 0 for left edge shaping and when OUT_HSTOP is less than OUT_HLEN_ACT for right edge shaping. A programmable flat matte colour background is inserted into the output non-live video. Note that the colour background is inserted prior to the matrix conversion. This means that the downloaded background colour is in the input colour space coordinates.
1 1 1 YMAT_IN +10 COLOUR DIFFERENCE OVERSAMPLE CBMAT_IN 9.0 CRMAT_IN 9.0 MATRIX F V H BLANK 1 1 1 1 +10 OUTPUT FORMAT +10 +10 Y_G_DATA_OUT CB_B_DATA_OUT CR_R_DATA_OUT
R_RAMP_OFF L_RAMP_OFF FILL Y_FROM_FILTER C_FROM_FILTER Y_FROM_MEMORY C_FROM_MEMORY +10 9.0 +10 9.0
YMAT_OUT +10 CBMAT_OUT 9.0 CRMAT_OUT 9.0
CK H_PROC_FIRST Y_BKGD CB_BKGD CR_BKGD 1 8 8 8 G1 G2 G3 B1 B2 B3 R1 R2 R3 OUT_8_BITS OUT_MODE 39 39 39 1 2 OUT_TRS_ON OUT_MODE CK_OUT 1 2 1
OUT_MODE 00 = 4:4:4 GBR TRIPLE OUTPUT 01 = 4:4:4 YCbCr TRIPLE OUTPUT 10 = 4:2:2 YCbCr MUXED SINGLE OUPUT 11 = 4:2:2 YCbCr MUXED DUAL OUTPUT
NOTE: All inputs from the serial interface enter from the bottom. All inputs from the output timing circuit enter from the top.
Figure 3-41: Output Processor Block Diagram
The matrix block performs the following operations:
G1 ( YMAT IN - 64 ) + G2 CBMAT IN + G3 CRMAT IN YMATOUT = -------------------------------------------------------------------------------------------------------------------------------------------- + 64 1024
B1 ( YMAT IN - 64 ) + B2 CBMAT IN + B3 CRMAT IN PBMATOUT = ------------------------------------------------------------------------------------------------------------------------------------------- + C OFFSET 1024
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GF9320 Data Sheet
R1 ( YMAT IN - 64 ) + R2 CBMAT IN + R3 CRMAT IN PRMAT OUT = ------------------------------------------------------------------------------------------------------------------------------------------- + C OFFSET 1024
where YMATIN, CBMATIN and CRMATIN are the inputs to the matrix; YMATOUT, CBMATOUT and CRMATOUT are the outputs of the matrix; and G1, G2, G3, B1, B2, B3, R1, R2 and R3 are the matrix coefficients; COFFSET is given by
C OFFSET = 64 OUT_MODE = 0 512 otherwise
and 1024 is the gain of the matrix. The matrix coefficients provide +6dB of range for gain adjustments. The Cb and Cr components at the input to the matrix are in 2's complement format. The B and R components at the output of the matrix are unsigned in GBR output mode (OUT_MODE=0) and are offset binary in YCbCr output mode (OUT_MODE=1, 2 or 3). The matrix coefficients are completely programmable and are downloaded as described in the 3.2 Serial Interface Control. The output format block formats the data into one, two or three channels according to the OUT_MODE parameter and inserts the output format TRS. If TRS is enabled, the data is clipped to 4 and 1019 for 10-bits or 1 and 254 for 8-bits.
3.7 Output Timing Control
The output timing and control block determines the output video data timing. This block contains horizontal and vertical counters based on the output format parameters. The output timing is adjusted relative to the reference by using the LINE_ADV and H_POS parameters. The output reference is either the input TRS (if OUT_REF = 0) or the OUT_FRST pin on the GF9320 (if OUT_REF = 1). This provides for internal or external lock capability. The LINE_ADV parameter advances the output video data by LINE_ADV output lines. The H_POS parameter delays the output video data by H_POS samples. The range of H_POS is one output line or OUT_HLEN_TOT samples. Only limited ranges of input / output timing relationships are available by using the GF9320. In general, there are 2 fields / frames of delay through the GF9320. It is not possible for the GF9320 to have an output timing relationship such that the last active output line occurs after the SDRAM field / frame switch point.
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GF9320 Data Sheet
4. Package Dimensions
A B C D E F G H J K L M N P R T U V WY 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P IN #1 1.27 33.02 35.00 0.20
AA AB AC AD AE AF AF AE AD AC AB AA
YW VU T R P NML K J H G F ED CB A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.75 0.15 (X 352)
35.00 0.20
0. 60 0. 10
Figure 4-1: Package Dimensions
1.40 + 0. 30/-0.20
33. 02
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GF9320 Data Sheet
5. Revision History
Version
7 6 5
ECR
134925 133502
Date
November 2004 June 2004 November 2002
Changes and / or Modifications
Corrections to address pins: ADDR_A[10:0], ADDR_B[10:0], ADDR_C[10:0], ADDR_D[10:0], BA_A, BA_B, BA_C and BA_D. Changed BOUT description. Changed template. Add OUT_VLIVE issue and workaround - Change RST, SIF_RST, CS, RAS, CAS and WE pin descriptions to active low. Make same changes throughout DS. -Make 60I->30i changes for consistency. Updating GF9320. Remove all "Preliminary & Confidential" water marks & references with the document. Correction required for both Figure 15 and the table titled "Output Signal Timing Specification". Correction to figure on page 2 & other improvements. Creating Preliminary Data Sheet.
4 3 2 1 0
May 2002 September 2001 July 2001 June 2001 June 2001
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in a development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale.
GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX TEL. +44 (0)1252 747 000 FAX +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright June 2001 Gennum Corporation. All rights reserved. Printed in Canada www.gennum.com
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